The present invention relates to a semiconductor device and to a manufacturing method for the same and to a collector structure in the rear surface of a semiconductor substrate wherein the semiconductor substrate has been converted to a thin film, and to a manufacturing method for the same.
In the field of a high voltage withstanding semiconductor device that controls a voltage exceeding several hundred volts, element characteristics wherein heat emission, that is to say, loss is suppressed are required because the current handled is great. In addition, as for a driving system of a gate that controls this voltage and current, a voltage drive element of which the driving circuit is small so that the loss therein is small is desirable.
In recent years, because of the above described reasons, an insulated gate bipolar transistor, that is to say, an IGBT, has come into wide use as an element wherein a voltage drive is possible and loss is small in this field. The structure of this IGBT is a structure wherein the impurity concentration of the drain is lowered so as to secure the withstanding voltage in a MOS (metal oxide semiconductor) transistor and the drain can be regarded as a diode in order to reduce the drain resistance.
Thus, a diode carries out a bipolar operation in an IGBT and, therefore, in the present application the source of the MOS transistor of an IGBT is referred to as an emitter and the drain is referred to as a collector.
A voltage of several hundred volts is applied between the collector and the emitter of an IGBT, which is a voltage drive element and which is controlled by the gate voltage of which the voltage is xc2x1 several volts to several tens of volts. In addition, in many cases an IGBT is used as an inverter, wherein the voltage between the collector and the emitter is low in the case that the gate is in the on condition so that a great amount of current flows while no current flows and the voltage between collector and the emitter is high in the case that the gate is in the off condition.
Since the operation of an IGBT is carried out conventionally in the above described mode, the loss is divided into constant loss, which is a product of current and voltage in the on condition, and switching loss at the time of transition wherein the on condition and the off condition are switched. The product of leak current and voltage in the off condition is so small that it can be ignored.
On the other hand, it is important to prevent breakdown of the element during an abnormal state such as, for example, in the case that the load is short circuited. In this case, the gate is turned on while the power source voltage of several hundred volts is applied between the collector and the emitter so that a large current flows.
In an IGBT having a structure wherein a MOS transistor and a diode are connected in series the maximum current is controlled by the saturation current of the MOS transistor. Therefore, the current control works even at the time of short circuiting, as described above, so that breakdown of the element due to heat emission of a constant period of time can be prevented.
FIG. 75 is a cross sectional view schematically showing the configuration of a semiconductor device according to a prior art. An IGBT is formed in a semiconductor substrate having a first main surface and a second main surface that are opposed to each other. A p-type body region 102 is formed on the first main surface side of an nxe2x88x92 silicon layer 101 and an n-type emitter region 103 and a p+ impurity diffusion region 106 are formed in the first main surface within this p-type body region 102.
A trench 101a for a gate is created so as to penetrate this n-type emitter region 103 and this p-type body region 102 and so as to reach to nxe2x88x92 silicon layer 101. A gate insulating film 104a is formed so as to extend along the inner surface of this trench 101a for a gate and a gate electrode 105a is formed so as to fill in trench 101a for a gate. An insulating film 122A made of an oxide film is formed on the upper surface of gate electrode 105a. 
This nxe2x88x92 silicon layer 101, n-type emitter region 103 and gate electrode 105a form an insulating gate type field effect transistor (here MOS transistor) having nxe2x88x92 silicon layer 101 as a drain and having n-type emitter region 103 as a source.
Insulating films 109 and 122B are formed above the first main surface and a contact hole 109a is created in these insulating films 109 and 122B so as to reach to the surface of n-type emitter region 103 and p+ impurity diffusion region 106. A barrier metal layer 110 is formed on the upper surfaces of insulating films 109 and 122B as well as on the inner surface of contact hole 109a and a silicide layer 121a is formed in a contact portion between barrier metal layer 110 and the semiconductor substrate. An emitter electrode 111 is formed above the first main surface so as to be electrically connected to n-type emitter region 103 and to p+ impurity diffusion region 106 via this barrier metal layer 110 and this silicide layer 121a. 
An n-type buffer region 107 and a p-type collector region 108 are formed on the second main surface side of nxe2x88x92 silicon layer 101. A collector electrode 112 made of, for example, an aluminum compound is electrically connected to this p-type collector region 108.
In such a semiconductor device according to the prior art, thickness t2 of the semiconductor substrate is 300 xcexcm to 400 xcexcm and, in some cases, is 500 xcexcm.
Next, a manufacturing method for the semiconductor device according to the prior art shown in FIG. 75 is described.
FIGS. 76 to 85 are schematic cross sectional views showing the steps, in order, of the manufacturing method for the semiconductor device according to the prior art. In reference to FIG. 76, first n-type buffer region 107 and nxe2x88x92 silicon layer 101 are formed above p-type semiconductor substrate 108 that becomes the collector region through an epitaxial growth method. p-type body region 102 is formed on the first main surface side of this nxe2x88x92 silicon layer 101 and insulating film 131 made of, for example, a silicon oxide film is formed on top of that.
In reference to FIG. 77, this insulating film 131 is patterned by means of conventional photomechanical technology and etching technology. This patterned insulating film 131 is used as a mask so that ion implantation, or the like, is carried out on p-type body region 102 and, thereby, n-type emitter region 103 is formed. After this, insulating film 131 is removed.
In reference to FIG. 78, a thermal oxide film 132 and a CVD (chemical vapor deposition) oxide film 133 are sequentially formed over the entirety of the first main surface and, after that, patterning is carried out. This patterned thermal oxide film 132 and CVD oxide film 133 are used as a mask so as to carry out anisotropic etching on the semiconductor substrate. Thereby, trench 101a for a gate is created so as to penetrate n-type emitter region 103 and p-type body region 102 and so as to reach to nxe2x88x92 silicon layer 101.
In reference to FIG. 79, processes such as isotropic plasma etching and sacrificial oxidation are carried out. Thereby, the opening and the bottom portion of trench 101a for a gate become rounded and unevenness of the sidewalls of trench 101a for a gate is made flat. Furthermore, a sacrificial oxide film 132a is formed so as to extend the inner surface of trench 101a for a gate and is integrated into thermal oxide film 102. After this, CVD oxide film 133, thermal oxide film 132 and sacrificial oxide film. 132a are removed.
In reference to FIG. 80, the surface of the semiconductor substrate is exposed as a result of this removal.
In reference to FIG. 81, gate insulating film 104a made of a silicon oxide film, or the like, is formed on the inner surface of trench 101a for a gate and on the first main surface of the semiconductor substrate. Furthermore, a conductive layer 105 made of a polycrystal silicon, or the like, to which phosphorus is introduced so as to have a high concentration is formed in the first main surface of the semiconductor substrate so as to fill in trench 101a for a gate. After this, this conductive layer 105 is removed until the upper surface of gate insulating film 104a is exposed.
In reference to FIG. 82, thereby, conductive layer 105 is allowed to remain so as to fill in trench 101a for a gate so that gate electrode 105a is formed. After this, insulating film 122A is formed on the upper surface of gate electrode 105a. 
In reference to FIG. 83, an insulating film 109 made of, for example, a silicate glass and an insulating film 122B made of a CVD oxide film are sequentially formed and, after that, are patterned so as to open contact hole 109a. 
In reference to FIG. 84, barrier metal layer 110 is formed over the entirety of the surface. After this, lamp annealing, or the like, is carried out and, thereby, silicide layer 121a is formed in a contact portion between barrier metal layer 110 and the semiconductor substrate. Emitter electrode 111 is formed on barrier metal layer 110.
In reference to FIG. 85, p-type collector region 108 is removed through polishing.
After this, collector electrode 112 is formed so as to be connected to p-type collector region 108 in the second main surface and the semiconductor device according to the prior art, shown in FIG. 75, is completed.
In the configuration shown in FIG. 75, p-type collector region 108 of a high concentration, which is thick, exists on the second main surface side of semiconductor substrate and, therefore, the injection efficiency of holes from the collector side (second main surface side) becomes high at the time when the device turns ON. Thereby, the lowering of the ON voltage (lowering of RON) can be implemented.
In the configuration shown in FIG. 75, however, a main current that flows when the device turns ON becomes very large and the saturation current becomes large and, as a result, the device itself cannot control the current and it is difficult to secure or increase the withstanding capacity against breakdown at the time of device operation with no load.
In addition, in the configuration shown in FIG. 75, p-type collector region 108 of a high concentration, which is thick, exists on the second main surface side and, therefore, the injection efficiency of holes from the collector side (second main surface side) at the ON time of the device becomes very high. Therefore, the switching loss increases at the time of turning off in the case that the voltage Vce between the collector and the emitter is high (in the case of switching at high voltage).
Furthermore, in the manufacturing method shown in FIGS. 76 to 85, p-type collector region 108 and n-type buffer region 107 exist on the second main surface side from the beginning of the process and n-type buffer region 107 and nxe2x88x92 silicon layer 101 are formed through epitaxial growth. Therefore, the substrate tends to become costly and freedom in thickness of the substrate is limited.
An object of the present invention is to provide a semiconductor device wherein the lowering of the ON voltage is implemented, wherein the withstanding capacity against breakdown is secured and wherein switching loss on the high voltage side can be reduced and to provide a manufacturing method for the same.
In addition, another object of the present invention is to provide a semiconductor device that can prevent negative effects, due to fluctuation during the process, on the device characteristics and to provide a manufacturing method for the same.
In addition, still another object of the present invention is to provide a manufacturing method for a semiconductor device wherein limitations on the freedom of the thickness of the substrate are lessened and that is useful for lowering the price.
A semiconductor device according to one aspect of the present invention is provided with: a semiconductor substrate having a first main surface and a second main surface that are opposed to each other; and an element that includes an insulating gate type field effect transistor portion having an insulating gate structure on the first main surface side and wherein a main current flows between the first main surface and the second main surface, wherein the thickness of the semiconductor substrate (thickness of nxe2x88x92 drift layer) is no less than 50 xcexcm and no greater than 250 xcexcm.
Here, in the present specification, the thickness of the semiconductor substrate and the thickness of the drift layer have the same meaning.
In accordance with a semiconductor device according to one aspect of the present invention, the thickness of the semiconductor substrate is made thinner than that in the prior art so that the resistance component in the thickness direction is reduced and an insulating gate type field effect transistor structure is provided in the first main surface in order to achieve the lowering of the ON voltage and, thereby, the lowering of the ON voltage (lowering of RON) can be implemented.
In addition, the thickness of the semiconductor substrate is no less than 50 xcexcm and no greater than 250 xcexcm and the device is provided with an insulating gate type field effect transistor structure that increases the withstanding capacity against breakdown and, therefore, the withstanding capacity against breakdown at the time of device operation can be secured and loss can be reduced.
In the case that the thickness of the semiconductor substrate is less than 50 xcexcm, the substrate is too thin and it is difficult to secure the withstanding capacity against breakdown at the time of device operation. In addition, in the case that the thickness of the semiconductor substrate exceeds 250 xcexcm, VON becomes high. Thereby, stationary loss EDC becomes great and it becomes difficult to reduce loss.
In the above described aspect, the insulating gate type field effect transistor portion preferably has a source diffusion region and a drain diffusion region of a first conductive type, and the source diffusion region of the first conductive type is formed in the first main surface and is opposed to the drain diffusion region sandwiching a body region of a second conductive type.
The present invention is preferably applicable to an element that has such an insulating gate type field effect transistor portion.
In the above described aspect, an impurity diffusion region of the second conductive type formed in the second main surface is preferably further provided wherein the impurity surface concentration in the second main surface of the impurity diffusion region is 5xc3x971015 cmxe2x88x923, or greater.
Thereby, a change in VON or in VCES over time can be restricted so that negative effects on device characteristics due to such changeover time can be prevented.
In the above described aspect, the diffusion depth of the impurity diffusion region from the second main surface is preferably 1 xcexcm, or less.
Thus, the impurity diffusion region can be thinly formed and, therefore, the thickness of the semiconductor substrate can be made thinner.
In the above described aspect, the impurity activation ratio in the impurity diffusion region is preferably 50%, or less.
Thereby, negative effects on device characteristics due to fluctuations in process conditions can be prevented.
In the above described aspect, the impurity diffusion region and the drain diffusion region preferably form a pn junction, the drain diffusion region has a first high concentration region of the first conductive type in a region that contacts the impurity diffusion region and the first high concentration region has an impurity concentration peak of a concentration, or lower, of an impurity concentration peak of the impurity diffusion region.
Thereby, the main junction leak characteristics are reduced, the withstanding voltage rises and the tail current of the IC waveform decreases at the time of turning off so that switching loss Eoff is reduced. In addition, there is an effect of the restriction of change in Eoff due to increase in VCE.
In the above described aspect, the first high concentration region is preferably positioned in a range of a depth of 2 xcexcm, or less, from the second main surface.
Thus, the first high concentration region can be shallowly formed and, therefore, the thickness of the semiconductor substrate can be made thinner.
In the above described aspect, a trench for a gate is preferably created in the first main surface of the semiconductor substrate, a gate electrode of the insulating gate type field effect transistor portion is filled in the trench for a gate and an upper surface of the gate electrode protrudes from the trench for a gate.
Thus, the present invention is preferably applicable to a trench MOS gate-type element.
In the above described aspect, a trench for a gate is preferably created in the first main surface of the semiconductor substrate, a gate electrode of the insulating gate type field effect transistor portion is filled in the trench for a gate and an upper surface of the gate electrode is shifted not toward the first main surface but, rather, toward the second main surface side.
Thus, the present invention is preferably applicable to a trench MOS gate-type element.
In the above described aspect, a source side electrode electrically connected to the source diffusion region is preferably further provided on the first main surface side.
Thereby, the potential of the source diffusion region can be adjusted via the source side electrode.
In the above described aspect, the semiconductor substrate preferably has a trench for a source side electrode in the first main surface and a conductive layer electrically connected to the source side electrode is filled in into the trench for a source side electrode.
Thus, a trench filled in with a conductive layer for the source potential is provided and, thereby, the effective gate width can be reduced so that an effect of suppression of the saturation current is obtained. In addition, because of the effect of the reduction of the saturation current, an arbitrary current can be held for a longer period of time than in the prior art when the device switches in the no-load condition. That is to say, there is an effect of suppression of the saturation current of the device and of an increase of withstanding capacity against breakdown. Furthermore, oscillation at the time of switching in the no-load condition can be suppressed.
In the above described aspect, a plurality of trenches of the same type as the trench for a source side electrode is preferably provided and each piece of the conductive layer that fills in the plurality of trenches for a source side electrode is integrally formed of a single layer.
Thereby, it becomes possible to fill in, integrally, a plurality of trenches for a source side electrode with a single layer.
In the above described aspect, the source side electrode is preferably formed in the first main surface, to which no trenches are provided, and a second high concentration region of the second conductive type is provided to the first main surface, to which no trenches are provided, so as to be electrically connected to the source side electrode.
Thus, a wide portion to which no trenches are provided can be secured and, thereby, the effective gate width can be reduced.
A semiconductor device according to another aspect of the present invention is provided with: a semiconductor substrate having a first main surface and a second main surface that are opposed to each other; and an element that includes an insulating gate type field effect transistor portion which has an insulating gate structure on the first main surface side and wherein a main current flows between the first main surface and the second main surface, wherein the element has an impurity diffusion region which is formed in the second main surface and of which the impurity activation ratio is no greater than 50%.
In accordance with the semiconductor device according to the other aspect of the present invention, negative effects on device characteristics due to fluctuations in process conditions can be prevented.
In the case that the impurity activation ratio of the impurity diffusion region exceeds 50%, the fluctuation in VON relative to the implantation amount in the collector layer becomes great and the fluctuation in VON relative to the fluctuation of the ion implantation amount becomes great and, therefore, device design becomes difficult.
In the above described other aspect, the impurity surface concentration of the impurity diffusion region in the second main surface is preferably no lower than 5xc3x971015 cmxe2x88x923.
Thereby, change in VON or in VCES over time can be restricted and negative effects on device characteristics due to such change over time can be prevented.
In the above described other aspect, the diffusion depth of the impurity diffusion region from the second main surface is preferably no greater than 1 xcexcm.
Thus, the impurity diffusion region can be thinly formed and, therefore, the thickness of the semiconductor substrate can be made thinner.
In the above described other aspect, the impurity diffusion region and the drain diffusion region of the insulating gate type field effect transistor portion preferably form a pn junction, the drain diffusion region has a first high concentration region of a first conductive type in a region that contacts the impurity diffusion region and the first high concentration region has an impurity concentration peak of a concentration, or lower, of an impurity concentration peak of the impurity diffusion region.
Thereby, the main junction leak characteristics are reduced, the withstanding voltage rises and the tail current of the IC waveform decreases at the time of turning off so that switching loss EOFF is reduced. In addition, there is an effect of the restriction of change in EOFF due to increase in VCE.
In the above described other aspect, the first high concentration region is positioned in a range of a depth of 2 xcexcm, or less, from the second main surface.
Thus, the first high concentration region can be formed shallowly and, therefore, the thickness of the semiconductor device can be made thinner.
In the above described other aspect, a trench for a gate is preferably created in the first main surface of the semiconductor substrate, in that a gate electrode of the insulating gate type field effect transistor portion is filled in the trench for a gate and an upper surface of the gate electrode protrudes from the trench for a gate.
Thus, the present invention is preferably applicable to a trench MOS gate-type element.
In the above described other aspect, a trench for a gate is preferably created in the first main surface of the semiconductor substrate, a gate electrode of the insulating gate type field effect transistor portion is filled in the trench for a gate and an upper surface of the gate electrode is shifted not toward the first main surface but, rather, toward the second main surface side.
Thus, the present invention is preferably applicable to a trench MOS gate-type element.
In the above described other aspect, a source side electrode electrically connected to the source diffusion region of the insulating gate type field effect transistor portion is preferably further provided on said first main surface side.
Thereby, the potential of the source diffusion region can be adjusted via the source side electrode.
In the above described other aspect, the semiconductor substrate preferably has a trench for a source side electrode in the first main surface and a conductive layer electrically connected to the source side electrode is filled in the trench for a source side electrode.
Thus, a trench filled in with a conductive layer for the source potential is provided and, thereby, the effective gate width can be reduced so that an effect of suppression of the saturation current is obtained. In addition, because of the effect of the reduction of the saturation current, an arbitrary current can be held for a longer period of time than in the prior art when the device switches in the no-load condition. That is to say, there is an effect of suppression of the saturation current of the device and of an increase of withstanding capacity against breakdown. Furthermore, oscillation at the time of switching in the no-load condition can be suppressed.
In the above described other aspect, a plurality of trenches of the same type as the trench for a source side electrode is preferably provided and each piece of the conductive layer that fills in the plurality of trenches for a source side electrode is integrally formed of a single layer.
Thereby, it becomes possible to fill in, integrally, a plurality of trenches for a source side electrode with a single layer.
In the above described other aspect, the source side electrode is preferably formed in the first main surface, to which no trenches are provided, and a second high concentration region of the second conductive type is provided to the first main surface, to which no trenches are provided, so as to be electrically connected to the source side electrode.
Thus, a wide portion to which no trenches are provided can be secured and, thereby, the effective gate width can be reduced.
A manufacturing method for a semiconductor device according to the present invention is provided with the following steps.
First, a semiconductor substrate of a first conductive type having a first main surface and a second main surface that are opposed to each other is prepared. Then, a body region of a second conductive type is formed in the first main surface of the semiconductor substrate. Then, a source diffusion region of the first conductive type is formed in the first main surface within the body region. Then, a gate electrode is formed so as to be opposed to, via a gate insulating film, the body region sandwiched between a region of the first conductive type of the semiconductor substrate, which becomes a drain diffusion region, and the source diffusion region. Then, the thickness of said semiconductor substrate is made to be no less than 50 xcexcm and no greater than 250 xcexcm by removing the second main surface of the drift layer (drain diffusion region) after the formation of an insulating gate type field effect transistor portion having the drain diffusion region, the source diffusion region and the gate electrode.
In accordance with the manufacturing method for a semiconductor device according to the present invention, the semiconductor substrate can be made thinner through polishing.
In addition, since the thickness of the semiconductor substrate is thinner than in the prior art, the resistance component in the thickness direction lowered so that the lowering of the ON voltage (lowering of RON) can be implemented.
In addition, the thickness of the semiconductor substrate is no less than 50 xcexcm and no greater than 250 xcexcm and the device is provided with an insulating gate type field effect transistor structure that increases the withstanding capacity against breakdown and, therefore, the withstanding capacity against breakdown at the time of device operation can be secured and loss can be reduced.
In the above described aspect, the step of forming an impurity diffusion region of the second conductive type in the second main surface of the semiconductor substrate after the removal of the second main surface is, preferably, further provided.
Thereby, the impurity diffusion region can be formed without undergoing a heat treatment applied during the process and, therefore, the impurity diffusion region can be formed shallowly vis-à-vis the second main surface. Thereby, the semiconductor substrate can be made thinner.
In the above described aspect, the impurity diffusion region is preferably formed through ion implantation.
Thereby, the impurity diffusion region can be formed under effective control.
In the above described aspect, the step of forming a high concentration region of the first conductive type having an impurity concentration higher than that of the drain diffusion region in the second main surface from which the drain diffusion region is removed by polishing is preferably further provided. The impurity diffusion region is formed in the second main surface so as to form, together with the high concentration region, a pn junction. The high concentration region has an impurity concentration peak of a concentration, or less, of an impurity concentration peak of the impurity diffusion region.
Thereby, the main junction leak characteristics are reduced, the withstanding voltage rises and the tail current of the IC waveform decreases at the time of turning off so that switching loss EOFF is reduced. In addition, there is an effect of the restriction of change in EOFF due to increase in VCE.
In the above described aspect, the high concentration region is preferably formed so as to be positioned in a range of a depth of no greater than 2 xcexcm from the second main surface.
Thus, the high concentration region can be shallowly formed and, therefore, the thickness of the semiconductor substrate can be made thinner.
In the above described aspect, the impurity diffusion region is preferably formed so that the impurity activation ratio becomes no greater than 50%.
Thereby, negative effects on device characteristics due to fluctuations in process conditions can be prevented.
In the above described aspect, the step of creating a trench for a gate in the first main surface of the semiconductor substrate is preferably further provided and the gate electrode is formed so as to be filled in the trench for a gate.
Thus, the present invention is preferably applicable to a trench MOS gate-type element.
In the above described aspect, the gate electrode is preferably formed so that an upper surface thereof protrudes from the trench for a gate.
Thus, the present invention is preferably applicable to a trench MOS gate-type element.
In the above described aspect, the gate electrode is preferably formed so that an upper surface thereof is shifted not toward the first main surface but, rather, toward the second main surface side.
Thus, the present invention is preferably applicable to a trench MOS gate-type element.
In the above described aspect, the step of forming a source side electrode electrically connected to the source diffusion region is preferably further provided on the first main surface side.
Thereby, the potential of the source diffusion region can be adjusted via the source side electrode.
In the above described aspect, the step of creating a trench for a source side electrode in said first main surface of said semiconductor substrate is preferably further provided and a conductive layer electrically connected to the source side electrode is formed so as to fill in the trench for a source side electrode.
Thus, a trench filled in with a conductive layer for the source potential is provided and, thereby, the effective gate width can be reduced so that an effect of suppression of the saturation current is obtained. In addition, because of the effect of the reduction of the saturation current, an arbitrary current can be held for a longer period of time than in the prior art when the device switches in the no-load condition. That is to say, there is an effect of suppression of the saturation current of the device and of an increase of withstanding capacity against breakdown. Furthermore, oscillation at the time of switching in the no-load condition can be suppressed.
In the above described aspect, a plurality of trenches of the same type as the trench for a source side electrode is preferably created and a conductive layer for the electrode of the same type as the source side electrode is formed in the first main surface and after that is patterned so as to fill in the plurality of trenches for the source side electrode and, thereby, each piece of the conductive layer that fills in the plurality of trenches for the source side electrode is integrally formed of a single layer.
Thereby, it becomes possibly to integrally fill in a plurality of trenches for the source side electrode with a single layer.